How ZK Hardware Acceleration Roadmap ZK Proof Startup Cysic Breakthrough
Key Points: Cysic, a zero knowledge hardware startup, has just completed a $6 million seed round led by Polychain Capital.
Cysic’s primary goal, is to provide hardware-accelerated services in support of the ZK project’s ZK-proof-generation process.
Cysic has already expressed its intention to partner some of the most important ZK projects. It will first provide MSM acceleration service for these projects.
Cysic is a leading industry-leading ZK hardware acceleration program. It designs advanced ASIC chips to reduce ZK-proof generation times. Cysic has assembled a top-class hardware design and engineering team and completed the FPGA-based POC designing work. The POC results show that Cysic’s ZK acceleration capability is already an industry-leading position. ABBDE invested in Cysic in the seedround. Other investors in this round include Polychain and A&T. Unfortunately, ZK proof generation is often difficult due to the limitations of existing ZK proof systems. The amount of calculations required to generate ZK proofs will increase exponentially as the project becomes more complex and larger. Scroll and zkSync are two examples of large-scale zkEVM/zkVM projects. It can take hours, if not days, to calculate ZK proofs if it uses CPU. Most projects in real business need to limit the time taken to generate ZK proofs. For most ZK projects, it is unacceptable to take more than an hour to compute, especially for expansion projects like zkEVM/zkVM. Furthermore, the computational complexity of ZK-proof generation is hard to reduce theoretically within the two year window before the ZK project officially launches. To ensure that the project is usable, the ZK party must adopt the technical solution to “accelerating the generation ZK proofs” in order to speed up the generation of ZKproofs to the second or minute level. The first method to accelerate ZK-proof generation using high-performance hardware is currently preferred. There are two main types of time-consuming calculations in ZK proof generation. NTT (Number Theoretic Transform), calculation based upon polynomials 2. MSM (Multi-Scalar Multiplication), calculations based on elliptic curves. The logic is quite simple2. The logic is simple. The logic is repeated many times. Parallelism is similar to Bitcoin Mining computing. Parallelism is similar to Bitcoin Mining computing. The ZK project party has the option to choose according to their actual needs: 1. Accelerate NTT calculation by itself or 2. Accelerate MSM calculation by itself. Accelerate MSM calculation alone. This paper is the first to examine zk hardware acceleration.
Note 2: Some literature/articles claim that FFT (Fast Fourier Transform), and MSM are the most time-consuming ZK proof generation methods. While the principles of FFT are similar to NTT, most cryptographic calculations in ZK are performed using finite fields (Finite Field). Therefore, NTT should be used. We therefore use the NTT as the standard for most academic articles.
What is hardware acceleration? The current ZK hardware acceleration solution can be compared to the mining solution. It is mainly implemented using the following three types:GPU
There are currently two main hardware acceleration options on the market: FPGA and GPU. It is relatively simple to implement acceleration schemes using GPU/FPGA. Most manufacturers will implement the GPU/FPGA solution first to get the market more quickly. Because of the high hardware cost of GPUs/FPGAs, their high power consumption and limited absolute performance, as well as the high price, most manufacturers will first implement the GPU/FPGA solution. The ASIC solution is an integral part of the ZK Hardware Acceleration ecosystem.
Acceleration services similar to selling mining machines by selling hardware (whole machine/chip).
As we have already mentioned, NTT and MSM calculations are not tightly coupled during the generation ZK proofs. Hardware acceleration service providers can offer the following three services depending on their service granularities: Dedicated NTT Acceleration (Dedicated NTT App Acceleration API/Hardware device)
Dedicated MSM Acceleration (dedicated MSM accelerator API/hardware device).
Accelerator that accelerates both MSM and NTT simultaneously.
For many years, the differences between Hardware Acceleration ProvidersNTT (or MSM) computing problems has been extensively studied. It is not easy for large manufacturers to make breakthroughs in computing theory within a short time frame. The technical differences between manufacturers are more about engineering realization capabilities, control over algorithm details, technology stack selection, cost control of hardware manufacturing, and product design capabilities. Customers will consider the following factors when choosing an acceleration vendor: The performance of the hardware/service, and the computing time of manufacturer under the same computing task.
The manufacturer’s computing costs are the hardware acceleration cost for the same computing task.
Easy use of the API/device.
Why should we invest in Cysic Cysic’s main purpose is to provide hardware acceleration services in support of the ZK project’s ZKproof generation process. California, USA and Mainland China. These founding members have a majority of their backgrounds from Ph. D.s from the Department of Computer Science of Top 20 Universities of the United States and chip design team of Institute of Computing Technology. The project code is SolarMSM. This stage has seen the POC verification for FPGA-based MSM calculation. SolarMSM will offer external services via SaaS at this stage. Cysic has already reached agreements with leading ZK project parties. They will provide testing services in the near future. Many industry experts have confirmed that SolarMSM is the top-tier company in the sector for accelerating MSM computing performance. The founders have strong technical backgrounds, and are experts in cryptography as well as hardware design. Under the guidance of Elaine Shi, an internationally renowned professor in cryptography, Dr. Leo graduated Cornell University. Under the tutelage of Elaine Shi, a world-renowned professor of cryptography, Leo graduated from Cornell University. SolarMSM can speed up the MSM computing task with an input size of 230 to a POC verification. This is the highest level of public data results in the sector and is currently 1-2 orders of magnitude better than the ZPrize champion performance. It can be developed and implemented quickly, which is 1-2 order of magnitude faster than the first ZPrize. This is an incredible speed advantage.
Cysic has a strong supply chain integration capability. The delivery time can be reduced by having the PCB, heat dissipation and power supply, as well as the chassis structure, all customized in parallel. This is a significant improvement on the industry standard of 2-3 months.
The POC at this stage also serves as an internal verification of Cysic’s hardware design/development work. Full machine verification using SolarMSM at high bandwidth and high power consumption can reduce the risk of future ASIC chips errors. Technology RoadmapCysic plans on providing a complete ASIC hardware acceleration system, including NTT/MSM computing. The project party has a two-stage R&D strategy. Phase 1: FPGA-based POCI. In the first phase, a POC version MSM and NTT acceleration based upon Xilinx’s public FPGA: SolarMSM. The MSM computing acceleration module is complete. The 230-scale MSM computation can be completed in less that one second. This is the fastest performance among all public FPGA-MSM hardware acceleration results. It also leads the competition by more then 1-2 orders of magnitude. SolarMSM will be the fastest MSM hardware acceleration record until ASIC chips are available. Cysic has signed cooperation agreements with several ZK projects. In the next few months, Cysic will complete the NTT computing acceleration module SolarNTT that is based on SolarMSM. SolarNTT will be deployed on the exact same server as SolarMSM to enable accelerated computing using the same large-scale FPGA interconnection network. These two sets will be combined through the high-speed interconnection architecture created by Cysic to create an all-in-one acceleration system, SolarZKP. SolarZKP will offer API services to the public through SaaS. Phase 2: 12nm ASICs Cysic will begin the 12nm ASIC design stage. The goal is to reach the computing power of one ASIC chip, which will allow for the same performance as the entire SolarZKP. This will also reduce the power consumption of one chip to two orders. For Layer-2 projects that are based on zkEVM/zkVM technology, their core requirement for hardware acceleration is the stable and fast generation of ZK proofs. They will therefore be more inclined to choose an integrated acceleration solution that is more stable and faster.
Some ZK projects are not sensitive to the time required to generate ZK proofs. They do not need to generate proofs at the fastest speed. Customers can choose to have MSM computing acceleration only or combine MSM and NTT computing from different service providers within a reasonable time to select the best price.
There are market risks and project development delays for ASIC-based ZK hardware acceleration projects. Project development delays and market risks are possible for ASIC-based ZK Hardware Acceleration projects. Project Development Delay Risk There is a relationship between the ZK project party, and the ZK manufacturer of the hardware acceleration. The ZK project party will choose the best available hardware acceleration solution in order to capture the market share for the ZK project. One of the most important considerations for the zkEVM/zkVM is being able provide L2 blockproofs stably. In the early stages of ZK, there will be some ZK project partners who will establish long-term partnerships with hardware acceleration vendors. A slow project development can result in a loss of market share. ASIC tape-out is at risk. Tape-out failures can be caused by chip manufacturer capacity constraints. This will cause project delays and market risk. The ZK party can be divided into two groups: the privacy category or the expansion category. For privacy projects, using hardware acceleration may reduce the risk of side-channel attacks to some extent, but considering privacy issues, privacy projects will be more cautious in choosing ZK hardware acceleration solutions, such as choosing to purchase hardware directly instead of Not via SaaS service.Competing project head competitionAt present, there are three powerful competitors in the industry, namely Supranational, Ulvantanna, and Auradine.SupranationalSupranational has entered the GPU-accelerated ZK track since 2019 and recently began to involve the FPGA/ASIC field. Supranational already has an open-source GPU-based acceleration system that is very robust and leading the industry. We expect Supranational to also have a commercial, closed-source solution that will offer better performance. Supranational was able to enter the market earlier due to its industry resources and strong cash flow. Its strength should not be underestimated.AuradineCompared with the Senior, the founding team has rich entrepreneurial experience and a platform of top manufacturers and capital.Other Hardware Acceleration TeamsThe rest of the teams, such as Ingonyama and Jump Crypto, entered the track before them, but their performance is not as good as that of SolarMSM at this stage, according to the public data.ZK project internal hardware acceleration teamAt present, in addition to dedicated hardware acceleration teams, many ZK project parties are also exploring hardware acceleration solutions internally, such as zkSync and Scroll.zkSynczkSync chooses GPU/FPGA acceleration solution. ZPrice published results that zkSync’s GPU solution takes 2.28 seconds for input scale of 226 MSM. This is less than a tenth of the Cysic SolarMSM solution’s performance (230 MSM calculation takes less that 1 second). Scroll and other academic institutions are also working together to find better solutions. Their latest research results were presented at ASPLOS 2023 which is the leading conference in the field computer architecture . As the leading zkEVM project, it is worth looking forward to and tracking their follow-up progress.References PipeZK: Accelerating Zero-Knowledge Proof with a Pipelined Architecture, ZhangYe FPGA Acceleration of Multi-Scalar Multiplication: CycloneMSM, JumpCrypto GZKP: A GPU Accelerated Zero-Knowledge ProofSystemDISCLAIMER: The Information on this website is provided as general market commentary and does not constitute investment advice. We encourage you to do your own research before investing.Join us to keep track of news: https://linktr.ee/coincuHaroldCoincu NewsTags: ABCDECysicScrollZKZK HardwareZK ProofzkEVMZksynczkVM